1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a mask generation technique for forming regularly spaced interconnect necessary for optimal planarization. The mask generation technique is applicable to the production of a mask which can produce interconnect on the first or subsequent interconnect levels, upon which a dielectric is placed and thereafter globally planarized through etchback or polish.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves placing numerous devices on a single monolithic substrate. Each device is electrically isolated from the others, but later in the fabrication sequence specific devices are electrically interconnected so as to implement desired circuit function. Interconnect of those devices often takes place on more than one elevational level, each level having a set of substantially coplanar interconnect conductors. The numerous levels of interconnect arranged above a monolithic substrate are generally referred to as a multilevel interconnect structure.
There are numerous challenges involved with producing a multilevel interconnected structure. One of the more complex problems involves planarizing the interlevel dielectric layers formed on each level of interconnect. There are typically two types of interlevel dielectrics: a metal interlevel dielectric and a polysilicon interlevel dielectric. The metal interlevel dielectric is formed upon metal interconnect, either the first, second or subsequent layers of metal within the multilevel interconnect structure. The polysilicon interlevel dielectric is formed only upon polysilicon interconnect, generally the first level of interconnect. Polysilicon or polycide is herein defined as gate polysilicon, local interconnect polysilicon or various other types of polycrystalline material possibly interposed between a pair of capacitor plates.
Planarization of an interlevel dielectric, whether a metal interlevel dielectric or a polysilicon interlevel dielectric, is a matter of degree. There are several types of planarization techniques ranging from minimal planarization (i.e., smoothing); intermediate planarization, involving only isolated or local planarization; or extensive planarization, involving global planarization. Smoothing entails merely lessening the step slopes at the dielectric surface while not significantly reducing the surface elevational disparity. On the other hand, local planarization substantially reduces if not eliminates entirely the elevational disparity in localized areas across the substrate. Global planarization, however, is designed for eliminating elevational disparity over the entire topography of the integrated circuit. As one can imagine, global planarization is extremely difficult to achieve on a multilevel interconnect structure having, for example, two or more levels of interconnect.
Most manufacturers have quantified the level of planarization, and have attributed a planarization factor generally described as "total indicated range" or TIR. If the planarization factor or TIR is small, then subsequent interconnect placed on the interlevel dielectric surface suffers from poor step coverage and generally cannot be accurately patterned due to photolithography depth-of-field limitations. Even though local planarization is achieved, absent global planarization, step coverage and depth-of-field limitations present themselves at the local/global juncture. For example, if a near sub-micron interconnect feature is to be patterned, the TIR, demonstrated as elevational disparity, must be less than 0.5 microns. For deep sub-micron features, the maximum TIR may be as small as 0.1 microns. Absent global planarization, such features cannot be readily obtained. In order to attempt global planarization, conventional planarization processes involve, inter alia, at three separate types of planarization. First, limited planarization is achieved through a sacrificial etchback technique. Sacrificial etchback involves depositing a sacrificial layer across the interlevel dielectric topography, and then removing a sacrificial layer at the same etch rate as the underlying dielectric. The sacrificial etchback technique is well documented, and is generally valid only for the planarization of dielectric topographies in which the underlying features are less than 10.0 microns apart. For large regions between trenches, the step height will not be reduced, since the sacrificial material on top of such features will be the same as the thickness over the adjacent trench. In an effort to overcome the shortcomings of sacrificial etchback, a planarization block masking technique is often used. In this procedure, a liquid material is applied and developed as a planarization film followed by a block mask used to expose and develop this film. The block mask is arranged to protect topography in wide low regions from subsequent etch material. Thus, the planarization block mask allows removal of elevationally high regions commensurate with the protected low regions. Unfortunately, the planarization block mask involves an additional lithography step and a mask which must be produced and aligned with the underlying topography.
A more recent planarization process called chemical-mechanical polishing ("CMP"), overcomes to some extent the limitations of sacrificial etchback and block masking. CMP involves the application of an abrasive slurry and a pad across the entire topography. CMP forces planarization of that topography commensurate with the planarity of the pad surface. Provided the pad surface is relatively flat, the surface would be translated to the interlevel dielectric surface. Unfortunately, however, when force is applied to the pad, the pad will oftentimes conform to the unevenness of that topography. Thus, while high elevational areas (or peaks) receive substantial polishing, low elevational areas (or valleys) are also slightly abraded and removed.
A better understanding of the problems inherent with CMP are illustrated in reference to FIGS. 1 and 2. FIG. 1 depicts a partial cross-section of a semiconductor topography 10. Topography 10 includes a substrate 12 having a level of interconnect 14 fashioned thereon. Interconnect 14 comprises a plurality of substantially coplanar conductors 14a, 14b, and 14c. A relatively small lateral space 16a is formed between conductors 14a and 14b, and a relatively large lateral space 16b is formed between conductors 14b and 14c. Spaces 16 causes a disparity in the upper surface of a subsequently deposited interlevel dielectric 18. Accordingly, dielectric 18 must be planarized in a subsequent processing step shown in FIG. 2.
FIG. 2 illustrates a planarization technique using, for example, CMP. Specifically, the upper surface of interlevel dielectric 18 receives the slurry and polishing pad. The polishing pad inherently flexes or conforms under pressure to the upper surface of dielectric 18, causing the polishing pad to attack and remove dielectric 18 upper surface in large space areas 16b. Accordingly, an upper surface which has large valley areas will retain those valley areas after CMP. An upper surface having, on the other hand, numerous small valley areas will be more optimally planarized in accordance with that shown herein below. It would be desirable, therefore, to reduce to zero the elevational disparity 20, shown in FIG. 2.
While a need exists for attaining global planarization in both large and small spaces, the need must apply to existing planarization processes. It would therefore be desirable to utilize existing planarization techniques, but with a focus upon achieving a more uniform interlevel dielectric upper surface prior to the planarization step. A more uniform dielectric upper surface which can be more readily planarized affords advantages of numerous levels of interconnect and thereby presents a more optimal multilevel interconnect structure. The interconnect structure and dielectric topographies must be equally applicable to either metal interlevel dielectric and polysilicon interlevel dielectric. Thus, an improved planarization process can be applied upon a dielectric upper surface arranged on the first level of interconnect (typically polysilicon) as well as subsequent levels (typically metal) to achieve an overall, globally planarized multilevel interconnect structure.